Students: Sandeep Venishetti (graduated, December 2007, now at Intel, Folsom)

Advances in reconfigurable hardware technology have made Field Programmable Gate Arrays (FPGAs) attractive for scientific computing. There is increasing demand for fast floating-point arithmetic support to make FPGAs a practical option for scientific computing applications. In existing FPGA based double precision floating point multiplication and division approaches, operational frequency of the design is bounded by the performance of mantissa stage. In this project we develop novel algorithms for double precision floating point multiplication, division and square root that are fully IEEE 754 compliant. Our approach carries performance benefits (delay complexity) similar to Wallace and Dadda algorithms from ASIC domain; and regular routing benefits similar to ripple carry array multiplier and carry save multipliers. Multiplication algorithm outperforms existing algorithm and IP Core based academic approaches in terms of optimal operational frequency and associated pipeline depth required to achieve that speed. While Xilinx Floating-Point Core does not support Denormal Numbers and treats all NaNs as Quiet NaNs our model is fully compliant with IEEE-754 standard. We then apply the same algorithm onto division by convergence technique to implement the division operation. Division algorithm outperforms algorithm and IP-Core based solutions in the academia as well as Xilinx LogiCORE solutions.

Publications:

• Sandeep Venishetti, Ali Akoglu, "Highly Parallel FPGA Based IEEE-754 Compliant Double-Precision Floating-Point Division", International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'08), July 2008, Las Vegas, NV
• S. Venishetti and A. Akoglu, "A highly parallel FPGA based IEEE-754 Compliant Double-Precision Binary Floating-Point Multiplication Algorithm", IEEE International Conference on Field-Programmable Technology 2007 (ICFPT'07), pp. 145-152, December 12- 14, 2007, Kitakyushu, Japan