2. FPGA CAD Tools, Wirelength Prediction Based FPGA CAD Flow

Students: Audip Pandit (graduated, December 2007, now at Intel, Oregon), Hanyu Liu, Lakshmi Easwaran

FPGA CAD tools require net length predictions to make informed decisions through clustering, placement and routing stages towards power, area or delay based design goals. Channel width - a routability indicator, can be expressed as a function of total length of external nets. Performance indicators such as critical path delay and power consumption can also be expressed in terms of individual net lengths. Unfortunately, there has been minimal work devoted to estimating individual net lengths early in the CAD flow. Typically, Rent's rule is used to generate a net length distribution or average for a design, but it cannot associate lengths with specific nets. We argue that net length is an important parameter not explored in this context. Several "structural metrics" have been found to possess strong predictive qualities in the ASIC domain. In this project we take a structural approach to predicting individual net lengths and explore the applications and benefits of individual net length prediction in the FPGA CAD flow, such as routability/performance enhancement and design space exploration. To our knowledge this is a first study in the application of these metrics in the FPGA CAD flow.

Publications:

• A. Pandit and A. Akoglu, "Net length based routability driven packing", IEEE International Conference on Field-Programmable Technology 2007 (ICFPT'07), pp. 225-232, December 12 - 14, 2007, Kitakyushu, Japan

Source Codes:

• Intrinsic Shortest Path Length based wirelenght prediction readme.txt and source code