1. Application Specific Hybrid Grained Reconfigurable Computing

Students: Ruchika Verma, Yang Song, Deepak Sreedharan (graduated, May 2008 now at TI, Texas), David Montgomery (graduated, May 2007)

Physical limitations have constrained the evolution of reconfigurable computing through generic and symmetrical architectures. As logic density of field programmable gate arrays (FPGAs) is outpacing Moore's law, reconfigurable computing platforms will have the capability to become self-contained, high-end computers. Reconfigurable processors like FPGAs have resulted with significant performance improvements in many applications such as video processing, cryptography and scientific algorithms because of their inherently parallel architecture. However, there is a tradeoff between the complexity of logic blocks and area efficiency in a reconfigurable processor. For fine-grained architectures (e.g. generic FPGAs), more logic blocks will be required to implement the circuit and routing area becomes excessive. Coarse-grained architectures (e.g. RAW[2], Garp, ChESS, DReAM PipeRench) decrease the total number of logic blocks and hence interconnect complexity is reduced by localizing the connections. However, coarse-grained architectures may suffer from under-utilization of logic resources because it is difficult to fully utilize the functionality provided within each processing element. To overcome the drawbacks of generic reconfigurable architectures, there is a need for exploiting parallelism at multiple levels under a single architecture through the combined use of both coarse-grain and fine-grain functional blocks. Such architecture will have processing elements that are heterogeneous in nature and will have the reconfigurability to switch between applications within that domain.

H.264
Motion estimation is the most compute intensive routine of H.264 video compression standard. In this project we introduce an application-specific hybrid coarse grained reconfigurable architecture with an intelligent network on chip (NoC) mechanism. This is the first reconfigurable architecture with NoC in the academia which supports both variable block size and multiple motion vector search algorithms (full, diamond, hexagon, big hexagon and spiral ) requirement of H.264 video codec. Our model is a hierarchical hybrid processing element based 2D architecture which supports reuse of data between the processing elements through NoC routers in order to reduce memory transactions. Our approach is based on a simple design principle which utilizes a high-level of parallelism with intensive data reuse. Results show that our design reduces the gate count by 7x compared to its ASIC counterpart which only supports full search method. Moreover, the design operates at a frequency comparable to ASIC based implementation while sustaining 30fps and more (HDTV) which is not achievable with existing architecture.

Publications:

• R. Verma, A. Akoglu, "A Coarse Grained and Hybrid Reconfigurable Architecture With Flexible NOC Router for Variable Block Size Motion Estimation", IEEE International Parallel & Distributed Processing Symposium , Miami, Florida, USA, April 14-15, 2008
  
• R. Verma and A. Akoglu, "A coarse grained reconfigurable architecture for variable size block motion estimation", IEEE International Conference on Field-Programmable Technology 2007 (ICFPT'07), pp. 81-88, December 12 -14, 2007, Kitakyushu, Japan

Cryptography
The IP Security Protocol (IPSec) offers enoromous flexibility to the users to decide upon the choice of encryption and hashing algorithms. Software-only implementations act as a bottleneck in sustaining the throughput of a high-speed network due to high computation density of cryptographic operations. Hardware implementations could have different ASIC units (one for each algorithm) implemented and activated based on the needs of the protocol. However this would result in huge area overhead. Hence, there is a need for application-specific reconfigurable hybrid architecture for this algorithm domain.
The computation pattern profiler tool is developed to extract the recurring instruction sequences which then form the processing elements of the target architecture. We apply this toolset onto the three encryption algorithms (Blowfish, T-DES, and DES) and three hashing algorithms (MD5, SHA-1, RIPEMD-160). We then develop two new hybrid architectures specifically tailored to the computation characteristics of the target algorithms. This is a bottom-up approach to derive the architecture as opposed to modeling it at high level with System-C like environment.

Publications:

• D. Sreedharan, A. Akoglu, "A Hybrid Processing element Based Reconfigurable Architecture for Hashing Algorithms", IEEE International Parallel & Distributed Processing Symposium Miami, Florida, USA, April 14-15, 2008
• D. Montgomery, A. Akoglu, "Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications", IEEE International Conference on Application -Specific Systems, Architectures and Processors, (ASAP 2007), 9-11 July 2007 Page(s):365 - 370, Montréal, Québec, Canada