.: Reconfigurable Computing Laboratory, Members

I am interested in exploring the design arena for application specific reconfigurable devices. Some of my past works include developing a design methodology for the development of mixed grain platform architecture for cryptography application. My present work involves the development of a reconfigurable architecture suited for H.264 application. Most of the existing works in this area are in ASIC domain and very little has been done with respect to reconfigurable computing domain. So, the main crux of the work is to support the swiftly changing multimedia application requirement with the characteristics of reconfiguration and achieve the performance and area comparable to ASIC architectures.

CV (word) / Personal Web Page

Critical missions like those involved in environments where it is difficult to provide human help (eg. space missions), have the risk of being grounded due to system failures. Failures can occur due to radiation effects, meteorite collisions, and a myriad of other reasons. One common failure is the breakdown of hardware components. SCARS (Self-Configurable Architecture for Reusable Space Systems) makes use of the highly reconfigurable nature of FPGAs (Field Programmable Logic Arrays) to recover from faults. I am involved in this project that strives to develop a completely autonomous system which detects and recovers from failures by itself - with no requirement for on-site human help. The system being developed heals at two level - first at the node level (on the same FPGA), failing which it heals at the network level (on another FPGA). A robust self-healing system would ensure a higher success rate in critical missions.

CV (pdf) / Personal Web Page

Compressed sensing is a new method in medical imaging which requires fewer samples than the Nyquist theorem to reconstruct an image. The problem is lesser samples take larger times for reconstruction. Therefore there is a significant necessity to speedup these image reconstructions. I am currently involved in the FPGA based implementation of Non equispaced Fast Fourier Transform (NFFT) My future work would be evaluation of the NFFT algorithm on the GPU.

CV (pdf) / Personal Web Page

Power dissipation is becoming a major concern in FPGA's now-a-days. I am currently working on the Power aware FPGA CAD tool, PTV-PACK to optimize it further for power reduction. Individual net lengths have been predicted to improve routability and performance. I am currently trying to use these predicted net lengths in the clustering stage of the power aware CAD flow in order to reduce the consumption of power.

CV (word) / Personal Web Page

I am currently working on the coarse grained reconfigurable architecture with its application on motion estimation of H.264. I adopt bit serial scheme to our previous architecture to enhance the performance. Our new approach outperforms bit parallel and bit serial architectures in terms of technology independent gate count, throughput and performance per gate, and operates at a frequency comparable to ASIC based implementation. I am programming with Verilog to simulate the whole architecture.

CV (pdf) / Personal Web Page

I am currently working on reconfiguring the Smith-Waterman protein alignment algorithm to be efficiently utilized on many-core architectures. Namely Compute Unified Device Architecture (CUDA) on the Nvidia Tesla C870 GPU. Our current approach outperforms serial and parallel implementations. I am programming with C and CUDA to map the algorithm to the GPU.

CV (pdf) / Personal Web Page

Reconfigurable devices such as FPGAs have the advantage of being highly adaptable. In the event of a partial system failure, an FPGA can be reprogrammed to adjust to the new and unexpected situation. Reconfigurable devices increase the odds of success without the overhead of excess redundancy. The advantages that FPGAs provide lend themselves well to the field of Control Systems. In fact, FPGAs are already being used to implement sequential, feedback and fuzzy logic controllers. My project will involve taking the best features FPGAs have available and applying them to the field of Control Systems.

CV (pdf) / Personal Web Page

My research interests are in the general area of Application Specific Coarse-Grained Reconfigurable Architecture, especially its applications in image and video processing. Different from the other researchers, I pay much more attention to the memory architecture and the data schedule algorithm. Currently, I am working on FPGA Based Image Reconstruction.

CV (pdf) / Personal Web Page

I am exploring the routability and timing-driven clustering. I use the non-uniform depopulation in the clustering stage to reduce both routing requirement and critical path delay. I have finished the implementation for the tool with C programming language. Now, Exciting result has come out.

CV (pdf) / Personal Web Page

Direct Simulation Monte Carlo (DSMC) on Graphics Processing Unit (GPU) using CUDA Development Platform on TESLA (Fall 2008)

CV (pdf) / Personal Web Page