Warp Power May Soon Add Extra Life to Your Cell Phone and iPod Batteries

Roman Lysecky is assistant professor in the Department of Electrical and Computer Engineering.

By Pete Brown - February 25, 2009, 11:04 am

Assistant Professor Roman Lysecky of the Department of Electrical and Computer Engineering has been awarded a grant of more than $400,000 by the National Science Foundation to develop high-performance customizable computer chips. 

Lysecky’s research will focus on the emerging field of warp processing, which uses high-performance computer chips called field-programmable gate arrays, or FPGAs.

Star Trek fans should note that Lysecky will not be setting up a “warp core” in his Embedded Systems Design Laboratory. Although warp processing certainly is about achieving very high speeds, it is also about achieving gains in power conservation, but exceeding the speed of light is not part of Lysecky’s research.

“The original focus of warp processing was strictly performance,” said Lysecky. “My research proposal expands warp processing into a new domain of low power.” Some systems don’t actually need to be faster. Putting a warp processor in a cell phone, for instance, would not improve call quality. “The chip in a cell phone is already fast enough,” said Lysecky. “Using a warp processor doesn’t improve the quality of the call itself, it just leaves a few idle cycles behind. However, from a power perspective, there is a noticeable impact in the form of extended battery life.”

Computer chips such as FPGAs are hardware, and hardware typically is not programmable. It just does what it was built to do. FPGAs, however, are computer chips that can be programmed after manufacture—hence “field-programmable.”

FPGAs work in a parallel fashion, which means they can execute thousands of instructions simultaneously. Software, on the other hand, works sequentially and executes instructions one after the other. “This is very efficient from a computational point of view,” said Lysecky. “We can give hardware the flexibility of software so that hardware can be programmed on the fly,” said Lysecky. “It takes a matter of seconds to configure how the chip will work.”

Warp processing allows hardware programming to be integrated into software development. This is significant because it reduces dependence on hardware designers, who are in short supply. “Warp processing hides FPGAs from software developers,” said Lysecky. “But it allows them to extract the power and performance inherent in hardware programming, which speeds up development, reduces cost, and creates better performing software that uses less energy.”

Lysecky was awarded the 5-year grant of $415,000 under the NSF’s prestigious Faculty Early Career Development (CAREER) Program. The program supports junior faculty who exemplify the role of teacher-scholars through outstanding research, excellent education and the integration of education and research.

In-Stat, a market research company based in Scottsdale, Ariz., predicted in a 2006 report that the global market for FPGAs would increase from $1.9 billion in 2005 to $2.75 billion by 2010. In-Stat estimates that communications and industrial applications will account for 77 percent of the market share.

University of Arizona College of Engineering