ECE474A

Digital Logic
Fall 2012
Designation: 
Required for ECE
Catalog Data: 

ECE 474A -- Computer-Aided Logic Design (3 units)
Description: Tabular minimization of single and multiple output Boolean functions, NMOS and CMOS realizations, synthesis of sequential circuits, RTL description, laboratory exercises.
Grading:  Regular grades are awarded for this course: A B C D E.
Identical to:  C SC 474A.
May be convened with:  ECE 574A.
Usually offered:  Fall.

Prerequisite(s): 
ECE274 or Concurrent registration ECE 274
Textbook(s): 

No required textbook. The instructor provides class notes/slides which are sourced from a variety of books including but not limited to the following: 

  • Logic Synthesis and Verification Algorithms, by Gary D. Hachtel and Fabio Somenzi, Springer, 2006 ; 
  • Logic Minimization Algorithms for VLSI Synthesis, by Robert K. Brayton, Gary D. Hathtel, C. McMullen, and Alberto L. Sangiovanni-Vincentelli, Kluwer Academic Publishers, 1984;
  • Introduction to Algorithms, by Thomas H. Cormen, Charles E. Leiserson, and Ronald L. Rivest, MIT Press, 1998;
  • Synthesis and Optimization of Digital Circuits, by Giovanni De Micheli, McGraw-Hill, 1994; Digital Design, by Frank Vahid, John Wiley & Sons, 2007;
  • Verilog for Digital Design, by Frank Vahid and Roman Lysecky, John Wiley and Sons, 2007.
Course Learning Outcomes: 

By the end of this course, the student will be able to:

  1. Understand the difference between heuristic and exact optimization methods, and be able to classify a variety of algorithms into these categories.
  2. Use the Quine-McCluskey tabular minimization technique for identifying all the prime implicants, and solve the covering problem using Petrick’s method to find an optimal two-level implementation, for both completely specified and incompletely specified logic functions.
  3. Use Quine-McCluskey with iterative and recursive consensus methods for identifying all the prime implicants (complete sum), and solve the covering problem using row/column dominance to find a minimal gate, two-level implementation, for both completely specified and incompletely specified logic functions.
  4. Understand how generalized optimization algorithms can be adapted to the logic minimization problem.
  5. Use Branch-and-Bound along with MIS to solve the covering problem.
  6. Understand Espresso’s representation of Boolean functions and basic operations on compact cubical format.
  7. Use Espresso’s Unate Complement, Complement, and Expand subprocedures.
  8. Understand a variety of scheduling algorithms, including ASAP, ALAP, Hu’s, LIST_L, LIST_R, and Force Directed.
  9. Understand a variety of methods used for resource sharing and binding.
  10. Understand the role of verification in CAD along with the different testing methods.
  11. Design logic minimization tools in C/C++ and output the resulting circuit implementation in Verilog or equivalent textual representation.  
Course Topics: 

 

  • Design and implementation of sequential circuits
  • Register-Transfer Level (RTL) Design
  • Optimization and Tradeoffs of combinational and sequential circuits
  • Exact and Heuristic Minimization of Two-Level Circuits
Class/Laboratory Schedule: 

 

Three 50-minute lecture sessions per week

Ten sets of practice problems (not collected)

Three programming projects, mixture of Verilog and C

Three in-class examinations plus a final examination.

Computer Usage: Verilog programming assignment with Xilinx ISE

C/C++ programming assignments

Relationship to Student Outcomes: 

(a) an ability to apply knowledge of mathematics, science, and engineering (HIGH)

(c) an ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability (MEDIUM)

(e) an ability to identify, formulate, and solve engineering problems (LOW)

(k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice. (HIGH)

Prepared by: 
Dr. Susan Lysecky
Prepared Date: 
1/10/13

University of Arizona College of Engineering